- L1 (Level 1) May DAC – Base Model – does not have HoloAudio Caps, does not have KTE caps. Basic specs/components. copper wiring. standard Schurter Gold fuse. comes with remote, DC cable, power cable.
- L2 (Level 2) May DAC – Moderate spec’d version – includes upgraded HoloAudio Caps, does not have KTE caps. standard dual mono dac. no dac model covers. copper wiring. standard Schurter Gold fuse. comes with remote, DC cable, power cable.
- L3 (Level 3) Kitsune Edition May DAC – Top Tier Model with all the options, hand selected modules, KTE exclusive Caps, HoloAudio Caps, Dac Module exclusive cover/shields, Silver wiring, Red Nano Fuse and many more mods/improvements. comes with remote, DC cable, power cable.
- The new generation of linear compensation technology solves the accuracy errors caused by resistor
tolerance, after compensation, reaching a variance of 0.00005% tolerance accuracy.
- Proprietary anti-jitter technology that provides a full amplitude of anti-jitter without increasing noise floor
and other undesirable effects.
- Based on this new generation of technology May “梅” can provide a SINAD of >115dB and a dynamic range
of >130dB, which represents the performance limit reached by today’s most advanced R2R architecture
- Using the ultimate performance of PLL+FIFO technology, provides 0.1Hz Third-Order low-pass ability to
inhibit jitter. It also uses a high-performance femtosecond VCXO as the PLL clock source. Under the premise
of being almost immune to the front-end jitter, it can also lock up to 1.5us-2us @ 1KHz signal with high
jitter. (It can lock up to 1.5us-2us @ 1kHz signal with high jitter on the premise of almost being immune
- Dual Mono DAC L/R channels are independently powered by their own dedicated transformer in the PSU
chassis. This provides better channel separation and more accurate sound stage.
- Official Support USB and I2S up to DSD1024 and PCM1.536MHz sample rate.
- The USB interface uses proprietary firmware with ultra-low latency, a highly reliable data transmission, ideal
USB eye pattern measurements that contributes to 2-4 times higher performance than official firmware.
- Two sets of independent HDMI-I2S input interfaces are provided, and each set of I2S has a four-way
independent circuit, as opposed to standard LVDS chip, making I2S clock signals subject to lower
interference and lower jitter. In addition, each group of I2S inputs can be configured with specific pinout
configuration, making it compatible with most of the HDMI-I2S digital devices on the market.
The May DAC (all three models) will also support DSD1024 native and PCM 1.536MHz output! Theoretically it can do DSD2048 and PCM 3.072Mhz however is untested at this time. Also, we have worked hard to reduce the common click noise with all dacs when switching from DSD to PCM. This sound click sound has been reduced significantly with a special circuit design. The May DAC has the new and exclusive USB Enhanced module (L2 and KTE ONLY) which has our FPGA with the new Titanis 2.0 and custom firmware to improve USB Eye Pattern and reduce latency to near zero as well as reduce jitter to very very low levels. The USB module has completely new code written to optimize performance and reduce latency significantly. Low frequency performance (-40db) is also improved. The “enhanced” USB xmos module is twice as powerful/capable as the one that is used in the Spring2.
New improved power supply circuit with high performance multi stage regulation circuit using Rubycon ZLH caps, Panasonic FC, Vishay Caps or L2/KTE models with our exclusive HoloAudio Branded Caps (KTE model unique custom proprietary caps to replace Vishay caps)
We are no longer using common LVDS chipset and are now using a custom 4way circuit that isolates each line which further improves sound quality. such as the MCLK is isolated from data line and this improves jitter spec. Also there are TWO i2s ports in the May dac. Each one can be individually configured pin outs to support all i2s products on the market.
The May and KTE version of the May DAC also is with a CNC machined aluminum remote control! Standard with all three models.
The KTE version has OCC copper wire replaced with 1.5mm pure silver wire. 1.5mm Silver wire is soldered direct to the pcbs with highest grade audio solder. Silver Rhodium Faston connectors used at IEC input.
The May is a DUAL mono DAC. so there is a dedicated Dac Module for Left Channel and a dedicated Dac Module for Right Channel. Also each channel is individually powered by it’s dedicated Otype FLATWIRE transformer found in all three models. We have found after careful testing this new transformer type outperforms ALL transformers we have ever tested to this date. Near zero leakage, improved dynamics and overall spectacular performance. They are handmade for this dac specifically and delivery world class performance you would expect.
May DAC also has a new screen on the front that appears the same as the Spring2 on initial glance…. Font size is bigger than Spring2 but smaller than Spring1. Also you can see the CD track-time information is displayed when using spdif inputs!!!. This is done by extracting additional data from SPDIF. This a part of CD red book standard but nobody notices this and often forgets this cool feature or doesn’t know how to extract the data!. This will lead a fashion for other DAC developer to support this feature… customers will surely love this feature albeit subtle. The screen is much better contrast and viewing angles and one of the first things one may notice.
The May also has a front power button now! It’s been a request by many customers and gone are the days of a good old reach around to get the dac to be turned on! As mentioned before above… The DAC has a soft start circuit!! So don’t fret, it takes a moment for it to charge up and pull power without blowing the fuse!! It actually uses the same exact value of fuse that our Spring1 and Spring2 has! But two transformers! If we don’t have a soft start a couple issues can happen… one being a blown fuse from power surge, and another simply having possible pop noises. No chance of these things happening. We have carefully designed the circuit to have a zero compromise design.
Technical Information about our Custom PLL circuit:
Now the May is implemented with femto clocks, and also new discrete ultra high performance voltage regulators. It has an advanced PLL (phase lock loop) circuit that is completely custom built for ultra high performance anti jitter performance. Even the highest levels of jitter are near eliminated which delivers world class performance. Using Crystek VXCO clocks that will take any incoming digital signal an reclock it to perfection! This feature can be enabled or disabled to test and prove it’s performance is truly spectacular. Note: this is NOT an off the shelf PLL, but it’s truly the most powerful PLL found in a DAC. Or at least to our knowledge it’s the most powerful PLL ever.. Spdif usually is a not a good protocol because it’s very old and dated! It was designed in 70s together with CD with Sony and Philips. As you may know, It encodes the data signal together with clock signal so it can be transferred by a one-core cable. It makes the cable easy to source, but to encode the data to clock at the transmit side and decode the clock from data at the receiving side, creates jitter. Toslink is a fiber glass version of SPdif. So Toslink adds even more jitter while doing electronic to photo and photo to electronic translation. So people will see clearly that I2S is usually better than SPDIF because I2S has 4 separate signal, 3 clocks 1 data. So it does not have encoding-decoding stuff thus has a better jitter performance. This is important to know this.
A common technique to improve the clock signal from SPDIF is PLL. A PLL is to use a local clock generator to track the source clock. You know jitter is actually a time deviation problem. For example, the fist period frequency is 44101Hz and the following second period is 44099Hz. Thus it has 2/44100 jitter. A PLL is to smooth the time deviation of clock. So after the PLL, it can be 44100.9-44099.1(this is a weak/poor performing PLL). Or it can be 44100.1-44099.9(this is a strong performance PLL). Usually, a SPDIF chip, like AK4118A, has an internal PLL. AK4118A is good chip compared to other spdif receiver chip and it marks 50ps jitter. It’s the best we can get from a commercial chip. But it’s far from ideal, and definitely not enough for a HiFi standard we are implementing in the May dac. So we need a significantly stronger performing PLL. If the PLL is strong enough, it can smooth the 44101-44009 source clock to 44100.00001-44009.99999(very close to ideal 44100-44100)
But to make a stronger PLL is not easy, it’s actually incredibly difficult. First you need a powerful local clock source. A fixed clock can’t be used because it need to be adjusted to follow source clock rate. A common solution to use a VCO(voltage controlled oscillator). VCO is made by resistors, capacitor and inductors. The cost is low but performance is not so great. So, a better solution is to use VCXO(Voltage controlled crystal oscillator), it uses crystal as oscillator and crystal is a far better oscillator. The VCXO we used in May is Crystek’s CVHD-957. This the best VCXO we can get now.
The second hard problem is, the data need to be synchronized with clock. For example, the source has 44101-44099 clock from SPdif, that also mean it has 44101 samples in first period and 44099 samples in second period. So a good local 44100-44100 clock will have to throw away one sample in first period and lack one sample in second period. An easy fix to it is to use digital filter to smooth the data and it calls ASRC, but ASRC actually modified the data. So after ASRC, the data is modified thus not bit perfect anymore. And digital filter can also generate time domain problems like ringing artifacts. So, a digital filter is not a good way to solve this problem, or you can say, it solve a problem by introduce another problem.
May uses a fifo buffer to store the extra one sample in first period and release it in second period. So it has no harm to data. The difficulty for this design is how to manage fifo buffer. It can be a problem when you have a long-term jitter. And long-term jitter is actually called low frequency phase noise in a frequency domain point of view. To explain it easily, let’s take a example, a long term jitter can be like this, 44101-44102-44103-44104-44105-44104-44103-44102-44101-44100-44099-44098-44097-44096-44095-44096-44097-44098-44099-44100. So you see, it will have 25 extra sample in first ten periods, so the fifo buffer need to able store enough of them and release it in next 10 periods.
So, as a result, May’s PLL’s corner frequency is set to 0.05-0.1Hz in 3-orders. Than means it can reduce a 10s long term jitter by 90%, 1s period jitter by 99%, 0.1s period jitter by 99.9%…… That maybe the most powerful PLL in this industrial. And the most important is, it won’t lose data, it can still locking the source while huge jitter comes in. When you compared other similar PLL in the industrial, you can see it simply unlock the signal when huge jitter comes in. So, in that way, it simply stop you from listening, it tells you there is a problem but not solve it.
I have attached 2 pictures. The AP equipment generate huge jitters to SPDIF(750ns, 1KHz). If the PLL turned off, you will see an very ugly spectrum that means the jitter distorted the analog signal badly. The other picture turn on the PLL, and you can see it beautifully removed almost all the jitters. Compared to other competitors PLL. They won’t remove the jitter so clean, and simply unlock the signal for more than 10ns jitters.